The invention relates to a circuit arrangement for reading out and regenerating items of information stored in one-transistor storage or memory elements. For read-out, storage elements addressed by the activation of a word line transfer an existing information charge into bit lines to which they are assigned, and wherein the bit lines influence inputs of read-out/regenerating amplifiers to which they are assigned.
Currently the most important problem in the field of storage development consists in increasing the storage density of semiconductor memorys. Previously the storage density was fundamentally determined by the sensitivity of the read-out/regenerating amplifiers, the charge transfer via the bit lines (governed by the ratio of storage cell capacity to bit line capacity), and the dimensions of the amplifier. In particular in order to improve the charge transfer, arrangements are known (see for example arrangements comprising threshold transistors, such as German Patent No. 23 09 192 and L. G. Heller et al: High Sensitivity Charge Transfer Sense Amplifier, Digest of Technical Papers 1975, IEEE International Solid-State Circuits Conference, page 112 (both incorporated herein by reference)). Charge transfer arrangements also are known comprising a resistance gate, such as K. Hoffmann: Continuously Charge-Coupled Random Access Memory, Digest of Technical Papers 1976, IEEE International Solid-State Circuits Conference, page 130 (incorporated herein by reference). A series of proposals for increasing the amplifier sensitivity have also been made.
By means of improvements of the above mentioned type, on the basis of the signal amplitude it is fundamentally possible to reduce the dimensions of one-transistor storage elements and allied arrangements--see for example A. F. Tasch et al: The Charge-Coupled RAM Cell, IEEE Transactions on Electron Devices, vol. Ed. 23, No. 2, February 1976, pages 126 (incorporated herein by reference)--to the minimum which is technologically possible. However, the minimum spacing from bit line to bit line accordingly becomes smaller than the corresponding dimension of the amplifier.